题解 | #使用3-8译码器①实现逻辑函数#

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
wire E ;
assign E = E3 & ~E2_n & ~E1_n;
assign  Y0_n = ~(E & ~A2 & ~A1 & ~A0);
assign  Y1_n = ~(E & ~A2 & ~A1 &  A0);
assign  Y2_n = ~(E & ~A2 &  A1 & ~A0);
assign  Y3_n = ~(E & ~A2 &  A1 &  A0);
assign  Y4_n = ~(E &  A2 & ~A1 & ~A0);
assign  Y5_n = ~(E &  A2 & ~A1 &  A0);
assign  Y6_n = ~(E &  A2 &  A1 & ~A0);
assign  Y7_n = ~(E &  A2 &  A1 &  A0);
     
endmodule

module decoder0(
   input             A     ,
   input             B     ,
   input             C     ,
   
   output wire       L
);
wire Y1,Y2,Y3,Y4,Y5,Y6,Y7;
decoder_38 U1(
    .A2(A),
    .A1(B),
    .A0(C),
    .E1_n(1'b0),
    .E2_n(1'b0),
    .E3(1'b1),
    .Y1_n(Y1),
    .Y2_n(Y2),
    .Y3_n(Y3),
    .Y4_n(Y4),
    .Y5_n(Y5),
    .Y6_n(Y6),
    .Y7_n(Y7)
);

assign L = !Y1 || !Y3 || !Y6 || !Y7;

endmodule

写出逻辑函数的真值表：

再和3-8译码器的真值表对应，可以得到L= ~Y1_n + ~Y3_n + ~Y6_n + ~Y7_n;