题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output validout
);
//*************code***********//
always@(posedge clk or negedge rst)begin
    if(!rst)
        out <= 5'd0;
    else begin
        case(sel)
            2'd0: 
                begin 
                    out <= 5'd0;
                    d1 <= d; //注意只有在sel=0的时候采集到的输入才有效，也就是说每隔4clk采样一次数据
                end
            2'd1: out <= d1[3:0] + d1[7:4];
            2'd2: out <= d1[3:0] + d1[11:8];
            2'd3: out <= d1[3:0] + d1[15:12];
        endcase
    end
end

assign validout = (sel!=0 && rst==1) ? 1'b1 : 1'b0;

//*************code***********//
endmodule