题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire [7:0] c_temp;
reg [7:0] c_reg;

always @(posedge clk or negedge rst_n)
	if(!rst_n)
		c_reg <= 8'd0;
	else
		c_reg <= c;

sub_mod sub_mod_0 (clk, rst_n, a, b, c_temp);
sub_mod sub_mod_1 (clk, rst_n, c_reg, c_temp, d);

endmodule

module sub_mod(
	input clk,
	input rst_n,
	input [7:0] a,
	input [7:0] b,

	output reg [7:0] c
);
always @(posedge clk or negedge rst_n)
	if(!rst_n)
		c <= 8'd0;
	else
		c = (a <= b) ? a : b;
endmodule