题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);

	reg data_edge;
	always @(posedge clk_fast or negedge rst_n) begin
		if (~rst_n) begin
			data_edge <= 0;
		end else begin
			if (data_in) begin
				data_edge <= ~data_edge;
			end else begin
				data_edge <= data_edge;
			end
		end
	end

	reg data_edge_br;
	reg data_edge_br2;
	reg data_edge_br3;
	always @(posedge clk_slow or negedge rst_n) begin
		if (~rst_n) begin
			data_edge_br <= 0;
			data_edge_br2 <= 0;
			data_edge_br3 <= 0;
		end else begin
			data_edge_br <= data_edge;
			data_edge_br2 <= data_edge_br;
			data_edge_br3 <= data_edge_br2;
		end
	end

	assign dataout = (data_edge_br2 & ~data_edge_br3) | (~data_edge_br2 & data_edge_br3);
			

endmodule

脉冲转换为边沿，对边沿打两拍，再边沿转换为脉冲。