题解 | #信号顺序调整#
信号顺序调整
https://www.nowcoder.com/practice/3f6db9ded7ca4de7981c0a826e924563
`timescale 1ns/1ns
module top_module(
input [15:0] in,
output [15:0] out
);
wire [3:0] a,b,c,d;
assign a = in[3:0];
assign b = in[7:4];
assign c = in[11:8];
assign d = in[15:12];
assign out = {d,c,b,a};
endmodule
查看11道真题和解析