题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
	reg [6:0] count75;
reg flag;
always @ (posedge clk or negedge rst_n) 
begin
    if(~rst_n) begin
        count75 <= 7'b0;
        flag <= 1'b0;
    end 
    else begin
        if(pass_request) begin
            if(count75 <= 7'd65)
                count75 <= 7'd65;
            else
                count75 <= count75 + 7'b1;
        end 
        else begin
            if(flag == 1'b0) begin
                if(count75 == 7'd2) begin
                    flag <= 1'b1;
                    count75 <= 7'b0;
                end 
                else begin
                    count75 <= count75 + 7'b1;
                end 
            end 
            else begin
                if(count75 == 7'd74)
                    count75 <= 7'b0;
                else
                    count75 <= count75 + 7'b1;
            end
        end 
    end 
end 

// 红、黄、绿
always @ (posedge clk or negedge rst_n) 
begin
    if(~rst_n) begin
        red <= 1'b0;
        yellow <= 1'b0;
        green <= 1'b0; 
    end 
    else begin
        if(count75 >=0 && count75 < 9 || count75 == 7'd74) begin
            if(flag == 1'b0 && count75 != 7'd2)
                red <= 1'b0;
            else
                red <= 1'b1;
            yellow <= 1'b0;
            green <= 1'b0;
        end 
        else if(count75 >=9 && count75 < 14) begin
            red <= 1'b0;
            yellow <= 1'b1;
            green <= 1'b0; 
        end
        else if(count75 >=14 && count75 < 74) begin
            red <= 1'b0;
            yellow <= 1'b0;
            green <= 1'b1;
        end 
        else begin
            red <= red;
            yellow <= yellow;
            green <= green;
        end 
    end 
end 

// 倒计时
reg [7:0] clock_t;
always @ (rst_n, pass_request, count75, flag) begin
    if(~rst_n) begin          
        clock_t = 8'd10;
    end 
    else begin
        if(count75 >=0 && count75 <= 9) begin
            clock_t = 8'd10 - count75;
        end 
        else if(count75 >=10 && count75 <= 14) begin
            clock_t = 8'd15 - count75;
        end
        else if(count75 >=15 && count75 <= 74) begin
            clock_t = 8'd75 - count75;
        end 
        else begin
            clock_t = clock_t;
        end 
    end 
end 

assign clock = clock_t;
endmodule