题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
reg [3:0] ram_reg[127:0];
reg [3:0] ram_data;
integer i;
always @ (posedge clk or negedge rst) 
begin
    if(~rst) begin
        for(i = 0; i < 128; i = i+1) begin
            ram_reg[i] <= 4'b0;
        end 
    end 
    else begin
        if(enb) begin    // write
            ram_reg[addr] <= w_data;
        end 
        else begin
            ram_reg[addr] <= ram_reg[addr];
        end 
    end 
end 

assign r_data = enb ? 4'b0 : ram_reg[addr];

//*************code***********//
endmodule