题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
	reg [3:0]num_tmp;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			num_tmp<=0;
		end
		else begin
			if(set)begin
				num_tmp<=set_num;
			end
			else begin
				num_tmp<=num_tmp+1;
			end
		end
	end
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			number<=0;
		end
		else begin
			number<=num_tmp;
			end
	end
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			zero<=0;
		end
		else begin
			zero<=(num_tmp==0);
		end
	end
endmodule