题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);
reg [4:0]cnt_bin;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt_bin<=0;
    end
    else begin
        cnt_bin<=cnt_bin+1;
    end
end

wire [3:0]bin;
assign bin = cnt_bin[4:1];
always@(gray_out,bin)begin
    gray_out[3] = bin[3];
    gray_out[2] = bin[3] ^ bin[2];
    gray_out[1] = bin[2] ^ bin[1];
    gray_out[0] = bin[1] ^ bin[0];
end
endmodule