题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter IDLE = 3'b001;
parameter S0   = 3'b010;
parameter S1   = 3'b100;

reg [2:0] cs, ns;
always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        cs <= IDLE;
    end
    else begin
        cs <= ns;
    end 
end 

always @ (d1, d2, d3, rst) 
begin
    if( ~rst ) begin
        ns = IDLE;
    end 
    else begin
        case( cs )
            IDLE : begin
                case({d1, d2, d3}) 
                    3'b000 : ns = ns;
                    3'b100 : ns = S0;
                    3'b010 : ns = S1;
                    3'b001 : ns = IDLE;
                    default : ns = IDLE;
                endcase
            end 
            S0 : begin
                case({d1, d2, d3}) 
                    3'b000 : ns = ns;
                    3'b100 : ns = S1;
                    3'b010 : ns = IDLE;
                    3'b001 : ns = IDLE;
                    default : ns = IDLE;
                endcase
            end 
            S1 : begin
                if({d1, d2, d3} == 3'b000)
                    ns = ns;
                else 
                    ns = IDLE;     
            end
            default : begin
                if({d1, d2, d3} == 3'b000)
                    ns = ns;
                else 
                    ns = IDLE;  
            end 
        endcase
    end 
end 

reg out1_reg;
reg [1:0] out2_reg;
always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        out1_reg <= 1'b0;
        out2_reg <= 2'b0;
    end
    else begin
        case(cs) 
            IDLE : begin
                if({d1, d2, d3} == 3'b001) begin
                    out1_reg <= 1'b1; 
                    out2_reg <= 2'd1; 
                end     
                else begin
                    out1_reg <= 1'b0; 
                    out2_reg <= 2'd0;
                end 
            end 
            S0 : begin
                case({d1, d2, d3}) 
                    3'b010 : begin
                        out1_reg <= 1'b1; 
                        out2_reg <= 2'd0; 
                    end 
                    3'b001 : begin
                        out1_reg <= 1'b1; 
                        out2_reg <= 2'd2; 
                    end 
                    default : begin
                        out1_reg <= 1'b0; 
                        out2_reg <= 2'd0; 
                    end 
                endcase
            end 
            S1 : begin
                case({d1, d2, d3}) 
                    3'b100 : begin
                        out1_reg <= 1'b1; 
                        out2_reg <= 2'd0; 
                    end 
                    3'b010 : begin
                        out1_reg <= 1'b1; 
                        out2_reg <= 2'd1; 
                    end 
                    3'b001 : begin
                        out1_reg <= 1'b1; 
                        out2_reg <= 2'd3; 
                    end 
                    default : begin
                        out1_reg <= 1'b0; 
                        out2_reg <= 2'd0; 
                    end 
                endcase     
            end
            default : begin
                out1_reg <= 1'b0; 
                out2_reg <= 2'd0;
            end 

        endcase
    end 
end 

always @ (posedge clk or negedge rst) 
begin
    if( ~rst ) begin
        out1 <= 1'b0;
        out2 <= 2'b0;
    end
    else begin
        out1 <= out1_reg;
        out2 <= out2_reg;
    end 
end	

//*************code***********//
endmodule