题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output wire match,
	output wire not_match
	);

	reg [6:0]reg_data;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			reg_data<=7'b000_0001;
		end
		else if(reg_data[6]==1'b1)begin
			reg_data<={6'b00_0001,data};
		end
		else begin
			reg_data<={reg_data[5:0],data};
		end
	end

	assign match=((reg_data[6]==1'b1)&&(reg_data[5:0]==6'b011100))?1:0;
	assign not_match = ((reg_data[6] == 1'b1) & (reg_data[5:0] != 6'b011100)) ? 1 : 0;

endmodule

一个很好的思路