题解 | #编写乘法器求解算法表达式#

`timescale 1ns/1ns

module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
	localparam MULT1 = 4'd12;
	localparam MULT2 = 4'd5;
    
	reg [8:0] c_tmp;
    wire [7:0] mult_tmp1;
	wire [7:0] mult_tmp2;

	always @ (posedge clk or negedge rst_n) begin
		if (~rst_n)
		  c_tmp <= 'b0;
		else
		  c_tmp <= mult_tmp1 + mult_tmp2;
	end

    assign c = c_tmp;

	Four_Bit_Mult
	U0_Four_Bit_Mult
	(
  	  .clk(clk),
  	  .rst_n(rst_n),
   	  .a(MULT1),
      .b(a),
  	  .result(mult_tmp1)
 	);

	Four_Bit_Mult
	U1_Four_Bit_Mult
	(
  	  .clk(clk),
  	  .rst_n(rst_n),
   	  .a(MULT2),
      .b(b),
  	  .result(mult_tmp2)
 	);

endmodule

module Four_Bit_Mult(
  input clk,
  input rst_n,
  input [3:0] a,
  input [3:0] b,
  output reg [7:0] result
);

always @ (posedge clk or negedge rst_n) begin
	if (~rst_n)
	  result <= 'b0;
	else
	  result <= (a[3] ? (b << 3) : 8'b0) + (a[2] ? (b << 2) : 8'b0) + (a[1] ? (b << 1) : 8'b0) + (a[0] ? b : 8'b0);
end

endmodule