题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
reg pulse_a;
reg pulse_b1;
reg pulse_b2;
reg dataout_temp;
always@(posedge clk_fast or negedge rst_n)begin
	if(!rst_n)begin
		pulse_a<=1'b0;
	end
	else if(data_in==1)
        pulse_a<=~pulse_a;
	else 
        pulse_a<=pulse_a;
end

always@(posedge clk_slow or negedge rst_n)begin
	if(!rst_n)begin
		pulse_b1<=1'b0;
		pulse_b2<=1'b0;
	end
	else begin 
	    pulse_b1<=pulse_a;
		pulse_b2<=pulse_b1;
	end
end

always@(posedge clk_slow or negedge rst_n)begin
	if(!rst_n)begin
		dataout_temp<=1'b0;
	end
	else begin 
	    dataout_temp<=pulse_b1^pulse_b2;
	end
end
assign dataout=dataout_temp;
endmodule