题解 | #RAM的简单实现#

//注意读 写不要一起，存在一起有效的情况
`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	reg [3:0] d_RAM [0:255];
	integer i;
	// always @(posedge clk or negedge rst_n)
	// 	if(!rst_n)
	// 		write_addr <= 0;
	// 	else if(write_addr == 'd7)
	// 		write_addr<='d7;
	// 	else
	// 		write_addr<= write_addr+1;

	// always @(posedge clk or negedge rst_n)
	// 	if(!rst_n)
	// 		read_addr <= 0;
	// 	else if(write_addr == 'd7)
	// 		read_addr<='d7;
	// 	else
	// 		read_addr<= write_addr+1;

	always @(posedge clk or negedge rst_n)
		if(!rst_n)begin
			for(i=0;i<255;i=i+1)
                d_RAM[i]<=0;
        end
        else if(write_en)
            d_RAM[write_addr]<=write_data;
	
	always @(posedge clk or negedge rst_n)
		if(!rst_n)
			read_data <='d0;
		else if(read_en)
			read_data<= d_RAM[read_addr];
		

endmodule