题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
    reg [3:0]memober[0:127];
    integer i;
    always@ (posedge clk or negedge rst)
        if(!rst)begin
            for(i=0;i<128;i=i+1)
                memober[i]<=0;
        end
        else if(enb)
            memober[addr]<=w_data;//写
        
    assign r_data = (!enb)?memober[addr]:'d0;//读

    
    


//*************code***********//
endmodule