题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

parameter idle=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6;

reg [3:0] state,n_state;
always@(*)
case(state)
idle:   n_state = s1;
s1:		n_state = s2;
s2:		n_state = s3;
s3: 	n_state = s4;
s4:		n_state = s5;
s5:		n_state = s6;
s6:		n_state = s1;
endcase

always@(posedge clk or negedge rst_n)
if(!rst_n)
state <= 0;
else
state <= n_state;

always@(posedge clk or negedge rst_n)
if(!rst_n)
data <= 0;
else if(n_state==s1 | n_state==s2 | n_state==s4)
data <= 0;
else if(n_state==s3 | n_state==s5 | n_state==s6)
data <= 1;

endmodule