题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );

parameter RST=0, GG=1, YY=2, RR=3;
reg [1:0] Q_state, D_state;

always@(*)
case(D_state)
RST:    Q_state = reg_clock==8 ? RR : RST;
GG:     Q_state = reg_clock==1 ? RR : GG;
YY:     Q_state = reg_clock==1 ? GG : YY; 
RR:     Q_state = reg_clock==1 ? YY : RR;
default:Q_state = RST;
endcase

always@(posedge clk or negedge rst_n)
if(!rst_n)
D_state <= RST;
else
D_state <= Q_state;

reg [7:0] reg_clock;
always@(posedge clk or negedge rst_n)
if(!rst_n)
reg_clock <= 10;
else begin
    if(reg_clock==1)
    case(D_state)
    GG,RST: reg_clock<=10;
    YY:reg_clock<=60;
    RR:reg_clock<=5;
    default:reg_clock<=10;
    endcase
    else if(pass_request & reg_clock>10 & D_state==GG)
    reg_clock<=10;
    else if(reg_clock==8'd8&&D_state==RST)
    reg_clock <= 8'd10;
    else
    reg_clock<=reg_clock - 1;
end
assign clock = reg_clock;

wire red_t = Q_state==RR;
wire yellow_t = Q_state==YY;
wire green_t = Q_state==GG;

always@(posedge clk or negedge rst_n)
if(!rst_n)
red <= 0;
else
red <= red_t;

always@(posedge clk or negedge rst_n)
if(!rst_n)
yellow <= 0;
else
yellow <= yellow_t;

always@(posedge clk or negedge rst_n)
if(!rst_n)
green <= 0;
else
green <= green_t;

endmodule

1. 顺序描述有问题，应该是红-黄-绿
2. 根据仿真，需要设置rst状态下clock为8

1.颜色的转化 Q_state, D_state

2.转换的条件 clock的变化。

clock的重置，其他时间clock-1