题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
	wire [7:0]	out_1;
	wire [7:0]	out_2;
	// wire [7:0]	out_3;

	compare compare_inst1(
		.clk(clk),
		.rst_n(rst_n),
		.in_a(a),
		.in_b(b),
		.out(out_1)
	);

	compare compare_inst2(
		.clk(clk),
		.rst_n(rst_n),
		.in_a(a),
		.in_b(c),
		.out(out_2)
	);

	compare compare_inst3(
		.clk(clk),
		.rst_n(rst_n),
		.in_a(out_1),
		.in_b(out_2),
		.out(d)
	);

endmodule

module compare(
	input clk,
	input rst_n,
	input  [7:0]	 in_a,
	input  [7:0]	 in_b,
	output reg [7:0] out
);
	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				out <= 8'd0;
			else if(in_a > in_b)
				out <= in_b;
			else 
				out <= in_a;
		end
endmodule