题解 | #256选1选择器#

`timescale 1ns/1ns

module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);
	// reg out_temp;
	// genvar i;
	// generate
	// 	for(i=0;i<=255;i=i+1)
	// 	begin:for_loop
	// 		assign out = in[i]; 
	// 	end
	// endgenerate
	// assign out = out_temp;
	reg out_reg;
	integer i;
			always@(*)
				for(i=0;i<=255;i=i+1)
				begin:loop
					case(sel)
						i: out_reg = in[i]; 
					endcase
				end

	assign out = out_reg;
endmodule