题解 | #信号顺序调整#

`timescale 1ns/1ns

module top_module(
    input [15:0] in,
    input clk,
    input rst_n,
    output reg [15:0] out
);

    reg [2:0] cnt;
    reg [15:0] out_reg;

    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            cnt <= 3'd0;
        else if(cnt == 3'd4)
            cnt <= 3'd0;
        else
            cnt <= cnt + 1'b1; 

    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                begin
                    out_reg <= 16'b0;
                    out <= 16'd0;
                end
            else if(cnt == 3'd4)
                out <= out_reg;
            else
                out_reg <= {in[3:0],out_reg[15:4]};
        end
endmodule