题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
//------------------反馈信号----------------------------------------//
	wire  	pulse_feedback;
//------------------将快时钟域下的脉冲信号展宽------------------------//
	reg 	data_in_reg;
	always@(posedge clk_fast or negedge rst_n)
		begin
			if(!rst_n)
				data_in_reg <= 1'b0;
			else if(data_in)
				data_in_reg <= 1'b1;
			else if(pulse_feedback)
				data_in_reg <= 1'b0;
		end
//----------------快时钟域下同步慢时钟信号定义---------------------//
	reg 	data_clk_slow_d1;
	reg 	data_clk_slow_d2;
	reg 	data_clk_slow_d3;
//----------------慢时钟域下同步快时钟信号定义---------------------//
	reg 	data_clk_fast_d1;
	reg 	data_clk_fast_d2;	
//------------------将快时钟域下的信号同步至慢时钟域--------------//
	always@(posedge clk_slow or negedge rst_n)
		begin
			if(!rst_n)
				data_clk_slow_d1 <= 1'b0;
			else	
				data_clk_slow_d1 <= data_in_reg;
		end
//---------------在慢时钟域下将展宽后的脉冲信号打两拍---------------//
	always@(posedge clk_slow or negedge rst_n)
		begin
			if(!rst_n)
				begin
					data_clk_slow_d2 <= 1'b0;
					data_clk_slow_d3 <= 1'b0;
				end
			else	
				begin
					data_clk_slow_d2 <= data_clk_slow_d1;
					data_clk_slow_d3 <= data_clk_slow_d2;
				end
		end
//------------------对延时两拍后的信号做上升沿检测作为脉冲信号输出-------------//
	assign data_out = data_clk_slow_d2 & ~data_clk_slow_d3;
//-----------------将在慢时钟域下打拍的信号同步至快时钟域做为反馈信号-------------//
	always@(posedge clk_fast or negedge rst_n)
		begin
			if(!rst_n)
				begin
					data_clk_fast_d1 <= 1'b0;
					data_clk_fast_d2 <= 1'b0;
				end
			else	
				begin
					data_clk_fast_d1 <= data_clk_slow_d1;
					data_clk_fast_d2 <= data_clk_fast_d1;
				end
		end
//---------对延时两拍后的信号做上升沿检测作为反馈信号给到dara_in_reg----------//
	assign pulse_feedback = data_clk_fast_d1 & !data_clk_fast_d2;
endmodule