题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
//为实现8.7倍分频，可用10个clock_out的总周期等于87个clk_in
//前3个clk_out为8分频，后7个clock_out为9分频
reg clk_out_reg;
reg [7:0]cnt;
reg [4:0]cnt_8,cnt_9;
always@(posedge clk_in  or negedge rst)begin
    if(!rst) cnt<=0;
    else begin
        if(cnt==M_N-1) cnt<=0;
        else cnt<=cnt+1;
    end
end
always@(posedge clk_in  or negedge rst)begin
    if(!rst) cnt_8<=0;
    else if( cnt > c89-1)cnt_8<=0;
    else begin
        if(cnt_8==div_e-1)cnt_8<=0;
        else cnt_8<=cnt_8+1;
    end 
end
always@(posedge clk_in  or negedge rst)begin
    if(!rst) cnt_9<=0;
    else if( cnt <= c89-1)cnt_9<=0;
    else begin
        if(cnt_9==div_o-1)cnt_9<=0;
        else cnt_9<=cnt_9+1;
    end 
end

always@(posedge clk_in or negedge rst)begin
    if(!rst)clk_out_reg<=0;
    else if(cnt<c89)begin
        if(cnt_8==0 |cnt_8==(div_e/2))clk_out_reg<=~clk_out_reg;
        else        clk_out_reg<=clk_out_reg;
    end
    else begin
        if(cnt_9==0 | cnt_9==(div_o-1)/2)clk_out_reg<=~clk_out_reg;//占空比为4/9
        else        clk_out_reg<=clk_out_reg;
    end
end
assign clk_out=clk_out_reg;
//*************code***********//
endmodule