题解 | #五到一选择器#

`timescale 1ns/1ns

module top_module( 
    input [3:0] a, b, c, d, e, 
    input [2:0] sel,
    output  [3:0] out );


  assign out = (sel == 3'b000)?a:( (sel == 3'b001)?b: ( (sel == 3'b010)?c: ( (sel == 3'b011)?d: (  (sel == 3'b100)?e:0 ) ) )   );

endmodule