题解 | #优先编码器电路①#

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

always @ (*) begin
    if(!I_n[8])
        Y_n = 4'b0110;
    else begin
        if(!I_n[7])
            Y_n = 4'b0111;
        else begin
            if(!I_n[6])
                Y_n = 4'b1000;
            else begin
                if(!I_n[5])
                     Y_n = 4'b1001;
                else begin
                    if(!I_n[4])
                        Y_n = 4'b1010;
                    else begin
                        if(!I_n[3])
                            Y_n = 4'b1011;
                        else begin
                            if(!I_n[2])
                                Y_n = 4'b1100;
                            else begin
                                if(!I_n[1])
                                    Y_n = 4'b1101;
                                else begin
                                    if(!I_n[0])
                                         Y_n = 4'b1110;
                                    else
                                        Y_n = 4'b1111;
                                end
                            end
                        end
                    end
                end
            end
        end
    end
end
endmodule