题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);
	reg pulse_a_reg;
	always@(posedge clka or negedge rst_n)
		begin
			if(!rst_n)
				pulse_a_reg <= 1'b0;
			else if(sig_a)
				pulse_a_reg <= ~pulse_a_reg;
			else if(~sig_a)
				pulse_a_reg <= pulse_a_reg;
		end

	reg pulse_a_reg_d0;
	reg pulse_a_reg_d1;
	reg pulse_a_reg_d2;

	always@(posedge clkb or negedge rst_n)
		begin
			if(!rst_n)
				begin
					pulse_a_reg_d0 <= 1'b0;
					pulse_a_reg_d1 <= 1'b0;
					pulse_a_reg_d2 <= 1'b0;
				end
			else 
				begin
					pulse_a_reg_d0 <= pulse_a_reg;
					pulse_a_reg_d1 <= pulse_a_reg_d0;
					pulse_a_reg_d2 <= pulse_a_reg_d1;
				end
		end

	assign sig_b = pulse_a_reg_d2 ^ pulse_a_reg_d1;
endmodule