题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c	<=	9'd0;
	else	
		c	<=	(select==2'd0)? a:(select==2'd1)? b:(select==2'd2)? (a+b):(select==2'd3)? (a-b):c; 

endmodule