题解 | 8线-3线优先编码器Ⅰ实现16线-4线优先编码器

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);

wire    GS_0;
wire    GS_1,EO_1;
wire    [2:0]   Y_0,Y_1;   

encoder_83  u0
(
   .  I  (A[7:0]),
   . EI  (EO_1),
   
   .  Y  (Y_0),
   . GS  (GS_0),
   . EO  (EO) 
);


encoder_83  u1
(
   .  I  (A[15:8]),
   . EI  (EI),
   
   .  Y  (Y_1),
   . GS  (GS_1),
   . EO  (EO_1) 
);

assign  L = GS_1? (Y_1+4'd8): GS_0? Y_0:4'd0;
assign  GS = GS_0 | GS_1;

endmodule