题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

wire	[3:0]	G;
wire	[3:0]	P;
wire	[4:1]	Ci;

assign	G = A_in & B_in;
assign	P = A_in ^ B_in;

assign	Ci[1] = G[0] | (P[0] & C_1);
assign	Ci[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C_1);
assign	Ci[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | ( P[2] & P[1] & P[0] & C_1 );
assign	Ci[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] &G[0]) | (P[3] & P[2] & P[1] & P[0] & C_1 );

assign	S = P[3:0] ^{Ci[3:1],C_1} ;

assign	CO = Ci[4];
endmodule