题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);


reg		level,level_1,level_2,level_3	;
always@(posedge clka or negedge rst_n)
	if(!rst_n)
		level	<=	1'b0;
	else	if(sig_a)
		level	<=	~level;
	else	
		level	<=	level;

always@(posedge clkb or negedge rst_n)
	if(!rst_n)
		begin
			level_1	<=	1'b0;
			level_2	<=	1'b0;
			level_3	<=	1'b0;
		end
	else
		begin
			level_1	<=	level;
			level_2	<=	level_1;
			level_3	<=	level_2;
		end

assign	sig_b = level_2 ^ level_3;
endmodule