题解 | #使用握手信号实现跨时钟域数据传输#

`timescale 1ns/1ns
module data_driver(
	input clk_a,
	input rst_n,
	input data_ack,

	output reg [3:0]data,
	output reg data_req
	);

reg data_ack_1,data_ack_2;
reg [2:0]   cnt;

always@(posedge clk_a or negedge rst_n)
    if(!rst_n)
        begin
            data_ack_1  <=  1'b0;
            data_ack_2  <=  1'b0;
        end
    else
        begin
            data_ack_1  <=  data_ack;
            data_ack_2  <=  data_ack_1;
        end

always@(posedge clk_a or negedge rst_n)
    if (!rst_n)
           data <= 4'd0;
    else if(data_ack_1 && !data_ack_2 && data == 4'd7)
           data <= 4'd0;
    else if(data_ack_1 && !data_ack_2)
           data <= data +1'b1;
    else
           data <= data;

always@(posedge clk_a or negedge rst_n)
    if (!rst_n)
        cnt <=  3'd0;
    else    if(data_ack_1 && !data_ack_2)
        cnt <=  3'd0;
    else    if(data_req)
        cnt <=  cnt;
    else
        cnt <=  cnt + 1'b1;

always@(posedge clk_a or negedge rst_n)
    if (!rst_n)
        data_req    <=  1'b0;
    else    if(cnt==3'd4)
        data_req    <=  1'b1;
    else    if(data_ack_1 && !data_ack_2)
        data_req    <=  1'b0;
    else
        data_req    <=  data_req;




endmodule

module	data_receiver
(
	input   wire               clk_b,
	input   wire               rst_n,
    input   wire    [3:0]       data,
    input   wire            data_req,

    output  reg  data_ack
);

reg data_req_1,data_req_2;
reg data_reg;

always@(posedge clk_b or negedge rst_n)
    if(!rst_n)
        begin
            data_req_1  <=  1'b0;
            data_req_2  <=  1'b0;
        end
    else
        begin
            data_req_1  <=  data_req;
            data_req_2  <=  data_req_1;
        end

always@(posedge clk_b or negedge rst_n)
    if(!rst_n)
        data_ack    <=  1'b0;
    else    if(data_req_1)
        data_ack    <=  1'b1;
    else
        data_ack    <=  1'b0;

always@(posedge clk_b or negedge rst_n)
    if(!rst_n)
        data_reg    <=  4'd0;
    else    if(data_req_1 && !data_req_2)
        data_reg    <=  data;
    else
        data_reg    <=  data_reg;





endmodule