题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	parameter S_0		=3'd0;
	parameter S_01		=3'd1;
	parameter S_011		=3'd2;
	parameter S_0111	=3'd3;
	parameter S_01110	=3'd4;
	parameter S_011100	=3'd5;
	parameter handle	=3'd6;

	reg [2:0] cs, ns;
	reg [5:0] stop;
	reg data_temp;

	always@(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			match <= 0;
			not_match <= 0;
			ns <= 3'd0;
			stop <= 6'b0;
		end
		else begin
			cs <= ns;
			data_temp <= data;
		end
	end


	always@(*) begin
		case(cs)
			S_0: 		{ns, stop[5]} = {S_01, 		data_temp};
			S_01: 		{ns, stop[4]} = {S_011, 	~data_temp};
			S_011: 		{ns, stop[3]} = {S_0111, 	~data_temp};
			S_0111: 	{ns, stop[2]} = {S_01110, 	~data_temp};
			S_01110: 	{ns, stop[1]} = {S_011100, 	data_temp};
			S_011100: 	{ns, stop[0]} = {S_0, 	data_temp};
		endcase
	end

	always@(*) begin
		if(cs==S_011100)	begin
			if (|stop) begin
			{match, not_match} = 2'b0_1;
			end
			else if (~&stop) begin
			{match, not_match} = 2'b1_0;
			end
			else begin
			{match, not_match} <= 2'b0_0;
			end
		end
		else begin
			{match, not_match} <= 2'b0_0;
		end
		end

	
endmodule