题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter IDLE=0,BIT1=1,BIT2=2,BIT3=3,BIT4=4;

reg [2:0] state,n_state;
always@(*)
case(state)
	IDLE:n_state = data?BIT1:IDLE;
	BIT1:n_state = ~data?BIT2:BIT1;
	BIT2:n_state = data?BIT3:IDLE;
	BIT3:n_state = data?BIT4:BIT2;
	BIT4:n_state = data?BIT1:BIT2;
endcase

always@(posedge clk or negedge rst)
if(~rst)
state<=0;
else
state<=n_state;

always@(posedge clk or negedge rst)
if(~rst)
flag<=0;
else if(state==BIT4)
flag<=1;
else
flag<=0;

//*************code***********//
endmodule