题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] cnt;
always@(posedge clk or negedge rst_n)
if(~rst_n)
cnt<=3'b0;
else if(valid_a&ready_a)
cnt<=(cnt == 3'd5) ? 'd0 : (cnt + 1'd1);

reg [5:0]shift_reg;
always@(posedge clk or negedge rst_n)
if(~rst_n)
shift_reg<=6'b0;
else if(valid_a&ready_a)
shift_reg<={data_a,shift_reg[5:1]};

always@(posedge clk or negedge rst_n)
if(~rst_n)
data_b<=6'b0;
else if(cnt==3'd5)
data_b<={data_a,shift_reg[5:1]};

always@(posedge clk or negedge rst_n)
if(~rst_n)
valid_b<=1'b0;
else if(cnt==3'd5)
valid_b<=1'b1;
else
valid_b<=1'b0;

always@(posedge clk or negedge rst_n)
if(~rst_n)
ready_a<=1'b0;
else
ready_a<=1'b1;

endmodule