题解 | #输入序列不连续的序列检测#

注意& data_valid判断 match的时候

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0]shift_reg;
always@(posedge clk or negedge rst_n)
if(~rst_n)
shift_reg<=4'b0;
else if(data_valid)
shift_reg<={shift_reg[2:0],data};

always@(posedge clk or negedge rst_n)
if(~rst_n)
match <= 1'b0;
else if({shift_reg[2:0],data}==4'b0110 & data_valid)
match <= 1'b1;
else
match <= 1'b0;

endmodule