题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg [5:0]shift_reg;
reg [2:0] cnt;
always@(posedge clk or negedge rst_n)
if(~rst_n)
shift_reg<=5'b0;
else
shift_reg<={shift_reg[4:0],data};

always@(posedge clk or negedge rst_n)
if(~rst_n)
cnt<=3'b0;
else if(cnt>=3'd5)
cnt<=3'b0;
else
cnt<=cnt+3'b1;

always@(posedge clk or negedge rst_n)
if(~rst_n)
match <= 1'b0;
else if({shift_reg[4:0],data}==6'b011100 & cnt==3'd5)
match <= 1'b1;
else
match <= 1'b0;

always@(posedge clk or negedge rst_n)
if(~rst_n)
not_match <= 1'b0;
else if({shift_reg[4:0],data}!=6'b011100 & cnt==3'd5)
not_match <= 1'b1;
else
not_match <= 1'b0;

endmodule

`timescale 1ns/1ns
module testbench();
 
    reg clk,rst_n;
    reg a;
    wire match,not_match;
    parameter CLK_PERIOD =2;
initial begin
    $dumpfile("out.vcd");
    $dumpvars(0,testbench);
    clk = 1;
    forever begin 
    #(CLK_PERIOD/2) clk = ~clk;
    end
 end
initial begin
    rst_n = 0;
    #2
    rst_n =1;
end
initial begin
    #2 a = 0;
    #2  a = 1;
    #2  a = 1;
    #2  a = 1;
    #2  a = 0;
    #2  a = 0;
    #2  a = 0;
    #2  a = 1;
    #2 a=0;
    #10  $finish;
end
 
sequence_detect dut(
    .clk(clk),
    .rst_n(rst_n),
 
    .data(a),
    .match(match),
    .not_match(not_match)
);
endmodule