题解 | #含有无关项的序列检测#

这题再用state就不合适了，因为011xxx110要判断第三个x来决定接下来是什么状态。还是很简单。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0]shift_reg;
always@(posedge clk or negedge rst_n)
if(~rst_n)
shift_reg<=9'b0;
else
shift_reg<={shift_reg[7:0],a};

always@(posedge clk or negedge rst_n)
if(~rst_n)
match <= 1'b0;
else if(shift_reg[8:6]==3'b011 & shift_reg[2:0]==3'b110)
match <= 1'b1;
else
match <= 1'b0;
  
endmodule

再附上tb.v

`timescale 1ns/1ns
module testbench();
 
    reg clk,rst_n;
    reg a;
    wire match;
    parameter CLK_PERIOD =2;
initial begin
    $dumpfile("out.vcd");
    $dumpvars(0,testbench);
    clk = 1;
    forever begin 
    #(CLK_PERIOD/2) clk = ~clk;
    end
 end
initial begin
    rst_n = 0;
    #2
    rst_n =1;
end
initial begin
    #2 a = 0;
    #2  a = 1;
    #2  a = 1;
    #2  a = 1;
    #2  a = 0;
    #2  a = 0;
    #2  a = 1;
    #2  a = 1;
    #2 a=0;
    #10  $finish;
end
 
sequence_detect dut(
    .clk(clk),
    .rst_n(rst_n),
 
    .a(a),
    .match(match)
);
endmodule