题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

parameter   IDLE    =   4'b0000,
            s0      =   4'b0001,
            s1      =   4'b0010,
            s2      =   4'b0100,
            s3      =   4'b1000;

reg [3:0]   cur_state,nxt_state;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cur_state   <=  IDLE;
    else
        cur_state   <=  nxt_state;

always@(*)
    if(!rst_n)
        nxt_state   <=  IDLE;
    else    case(cur_state)
    IDLE:   nxt_state   <=  (din)?  s0:IDLE;
    s0  :   nxt_state   <=  (din)?  s1:IDLE;
    s1  :   nxt_state   <=  (din)?  s1:s2  ;
    s2  :   nxt_state   <=  (din)?  s3:IDLE;
    s3  :   nxt_state   <=  (din)?  s0:IDLE;
    default:    nxt_state   <=  IDLE;
    endcase

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        Y   <=  1'b0;
    else    if(cur_state==s3)
        Y   <=  1'b1;
    else
        Y   <=  1'b0;

endmodule