题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p
(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0]   cnt_bit;
reg [4:0]   data_reg;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt_bit <=  3'd0;
    else    if(cnt_bit==3'd5 && ready_a)
        cnt_bit <=  3'd0;
    else    if(valid_a && ready_a)
        cnt_bit <=  cnt_bit + 1'b1;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        valid_b <=  1'b0;
    else    if(cnt_bit == 3'd5 && ready_a)
        valid_b <=  1'b1;
    else
        valid_b <=  1'b0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_reg    <=  5'd0;
    else    if(valid_a && ready_a)
        data_reg[cnt_bit]   <=  data_a;
    else    if(cnt_bit == 3'd5 && valid_a)
        data_reg    <=  5'd0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_b  <=  5'b0;
    else    if(cnt_bit==3'd5 && valid_a &&ready_a)
        data_b  <=  {data_a,data_reg};

always@(posedge clk or negedge rst_n)
    if(!rst_n)
		ready_a	<=	1'b0;
	else
        ready_a <=  1'b1;


endmodule