题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg [3:0]   bit_cnt;

always@(posedge clk_in or negedge rst)
    if(!rst)
        bit_cnt <=  4'd3;
    else    if(bit_cnt == 4'd7)
        bit_cnt <=  4'd0;
    else
        bit_cnt <=  bit_cnt + 1'b1;

assign  clk_out2 = ~bit_cnt[0];
assign  clk_out4 = ~bit_cnt[1];
assign  clk_out8 = bit_cnt[2];

//*************code***********//
endmodule