题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0]   bit_cnt;
reg     out_reg,reg_out;
always@(posedge clk_in or negedge rst)
    if(!rst)
        bit_cnt <=  3'd0;
    else    if(bit_cnt==3'd6)
        bit_cnt <=  3'd0;
    else
        bit_cnt <=  bit_cnt + 1'b1;


always@(posedge clk_in or negedge rst)
    if(!rst)
        reg_out <=  1'b0;
    else    if(bit_cnt  ==  3'd3)
        reg_out <=  1'b1;
    else    if(bit_cnt  == 3'd6 )
        reg_out <=  1'b0;

always@(negedge clk_in or negedge rst)
    if(!rst)
        out_reg <=  1'b0;
    else    if(bit_cnt  ==  3'd3)
        out_reg <=  1'b1;
    else    if(bit_cnt  == 3'd6 )
        out_reg <=  1'b0;

assign  clk_out7 = (out_reg || reg_out);
//*************code***********//
endmodule