题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);
parameter	s0 	=	4'b0001,
			s1	=	4'b0010,
			s2	= 	4'b0100,
			s3  =	4'b1000;

reg	[3:0]	cur_state;					
reg	[3:0]	nxt_state;

always@(posedge	clk or negedge rst)
	if(!rst)
		cur_state	<=	s0;
	else
		cur_state	<=	nxt_state;

always@(*)
	case(cur_state)		
		s0:
			begin
				nxt_state	<=	s1;
			end
		s1:
			begin
				nxt_state	<=	s2;
			end
		s2:
			begin
				nxt_state	<=	s3;
			end	
		s3:
			begin
				nxt_state	<=	s0;
			end
		default:
			begin
				nxt_state	<=	s0;
			end	
	endcase	

always@(*)
	case(cur_state)	
		s0,s2,s3:
			begin
				clk_out	<=	1'b0;
			end	
		s1:
			begin
				clk_out	<=	1'b1;
			end

		default:
				clk_out	<=	1'b0;
	endcase

endmodule