题解 | #流水线乘法器#

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
//输入数据寄存
reg [size-1:0] mul_a_reg;
reg [size-1:0] mul_b_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    begin
			mul_a_reg <= 'b0;
			mul_b_reg <= 'b0;
		end
	else 
	    begin
			mul_a_reg <= mul_a;
			mul_b_reg <= mul_b;
		end

//单bit数据乘法后的寄存
wire [size*2-1:0] temp [size-1:0];

assign temp[0] = mul_b_reg[0] ? {4'b0,mul_a_reg} : 'd0;
assign temp[1] = mul_b_reg[1] ? {3'b0,mul_a_reg,1'b0} : 'd0;
assign temp[2] = mul_b_reg[2] ? {2'b0,mul_a_reg,2'b0} : 'd0;
assign temp[3] = mul_b_reg[3] ? {1'b0,mul_a_reg,3'b0} : 'd0;

//数据输出
always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    mul_out <= 'd0;
	else 
	    mul_out <= temp[0] + temp[1] + temp[2] + temp[3];

endmodule