题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,

 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg flag;//flag为0时进行8分频，flag为1时进行9分频
reg [7:0]cnt;//87个周期计数器
reg [4:0]clk_cnt;//偶分频和奇数分频计数器，为了给flag辛哈赋值
reg clk_out_r;

always@(posedge clk_in or negedge rst)
    if (rst == 1'b0)
        cnt <= 8'b0;
    else if (cnt == M_N - 1'b1)
        cnt <= 1'b0;
    else 
        cnt <= cnt + 1'b1;

always@(posedge clk_in or negedge rst)
    if (rst == 1'b0)
        flag <= 1'b0;
    else if (cnt == c89 - 1'b1 || cnt == M_N - 1'b1)
        flag <= ~flag;
    else 
        flag <= flag;

always@(posedge clk_in or negedge rst)
    if (rst == 1'b0)
        clk_cnt <= 5'b0;
    else if (flag == 1'b0 && clk_cnt == div_e - 1'b1)
        clk_cnt <= 5'b0;
    else if (flag == 1'b1 && clk_cnt == div_o - 1'b1)
        clk_cnt <= 5'b0;
    else 
        clk_cnt <= clk_cnt + 1'b1;

always@(posedge clk_in or negedge rst)
    if (rst == 1'b0)
        clk_out_r <= 1'b0;
    else if (flag == 1'b0)
        clk_out_r <= (clk_cnt <= 3'd3) ? 1'b1 : 1'b0;
    else if (flag == 1'b1)                              //小数分频对占空比没有要求
        clk_out_r <= (clk_cnt <= 3'd3) ? 1'b1 : 1'b0;
    else 
        clk_out_r <= clk_out_r;

assign clk_out = clk_out_r;

//*************code***********//
endmodule