题解 | #简易秒表# 《一种较为简洁的写法，判断语句嵌套》

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
	
always@(posedge clk or negedge rst_n) begin
	if(~rst_n)
		second	<= 'd0;
	else
		second	<= (minute==60)? 'd0 : (second == 60)? 'd1: (second + 1'b1);
end

always@(posedge clk or negedge rst_n) begin
	if(~rst_n)
		minute	<= 'd0;
	else
		minute	<= (minute==60)? 'd0 : (second == 60)? (minute + 1'b1): minute;
end
	
endmodule

一种较为简洁的写法，判断语句嵌套