题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

parameter sta0 = 2'b00;
parameter sta1 = 2'b01;
parameter sta2 = 2'b10;
parameter sta3 = 2'b11;

reg [1:0] stage, next_stage;

always@(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        stage       <= sta0;
    end else begin
        stage       <= next_stage;
    end
end

always@(*) begin
    case(stage)
    sta0: begin
        if(C)
            next_stage  = sta1;
        else
            next_stage  = sta0;
    end

    sta1: begin
        if(C)
            next_stage  = sta1;
        else
            next_stage  = sta3;
    end

    sta2: begin
        if(C)
            next_stage  = sta2;
        else
            next_stage  = sta0;
    end

    sta3: begin
        if(C)
            next_stage  = sta2;
        else
            next_stage  = sta3;
    end
    endcase
end

assign Y = (((stage==sta2)&C) | (stage==sta3));




endmodule