题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0]data_cnt;
reg [119:0]data_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_cnt <= 4'b0;
	else if (valid_in == 1'b1)
	    data_cnt <= data_cnt + 1'b1;
	else 
	    data_cnt <= data_cnt;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_reg <= 120'b0;
	else if (valid_in == 1'b1)
	    data_reg <= {data_reg[95:0],data_in};
	else 
	    data_reg <= data_reg;
//输出有效信号赋值
always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    valid_out <= 1'b0;
	else if (data_cnt == 4'd5 && valid_in == 1'b1)
	    valid_out <= 1'b1;
	else if (data_cnt == 4'd10 && valid_in == 1'b1)
	    valid_out <= 1'b1;
	else if (data_cnt == 4'd15 && valid_in == 1'b1)
	    valid_out <= 1'b1;
	else 
	    valid_out <= 1'b0;
//输出数据赋值
always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_out <= 128'b0;
	else if (valid_in == 1'b1 && data_cnt == 4'd5)
	    data_out <= {data_reg,data_in[23:16]};         //注意数据是怎么进行拼接的！！！！！！！！
	else if (valid_in == 1'b1 && data_cnt == 4'd10)
	    data_out <= {data_reg[111:0],data_in[23:8]};
	else if (valid_in == 1'b1 && data_cnt == 4'd15)
	    data_out <= {data_reg[103:0],data_in};
	else 
	    data_out <= data_out;
	    
endmodule