题解 | #单端口RAM#
单端口RAM
https://www.nowcoder.com/practice/a1b0c13edba14a2984e7369d232d9793
`timescale 1ns/1ns
module RAM_1port(
input clk,
input rst,
input enb,
input [6:0]addr,
input [3:0]w_data,
output wire [3:0]r_data
);
//*************code***********//
reg [3:0] MEM [0:127] ;
integer i ;
always @(posedge clk or negedge rst) begin
if(!rst) begin
for(i=0;i<127;i=i+1)
MEM[i] <= 4'b0 ;
end
else if(enb)begin
MEM[addr] <= w_data ;
end
end
assign r_data = (!enb)? MEM[addr] : 4'b0 ;
//*************code***********//
endmodule
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