题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg     [2:0]   cnt;
reg     [2:0]   cnt_n;
reg             clk_p ;
reg             clk_n ;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        cnt <= 3'b0 ;
    end
    else if(cnt == 3'd4) begin
        cnt <= 3'b0 ;
    end
    else begin
        cnt <= cnt + 3'b1 ;
    end
end

always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk_p <= 1'b0 ;
    end
    else if(cnt == 3'd0) begin
        clk_p <= 1'b1 ;
    end
    else if(cnt == 3'd2) begin
        clk_p <= 1'b0 ;
    end
end

assign clk_out5 = clk_p ;
//*************code***********//
endmodule