题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
reg		[2:0]	cnt ;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		cnt <= 3'b0 ;
	end
	else if(d1) begin
		cnt <= cnt +3'b1 ;
	end
	else if(d2) begin
		cnt <= cnt + 3'd2 ;
	end
	else if(cnt >= 3'd3 && !sel) begin
		cnt <= 3'd0 ;
	end
	else if(cnt >= 3'd5 && sel) begin
		cnt <= 3'd0 ;
	end
end
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		out1<= 1'b0 ;
	end
	else if(cnt >= 3'd3 && !sel) begin
		out1 <= 1'd1 ;
	end
	else begin
		out1<= 1'b0 ;
	end 
end
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		out2<= 1'b0 ;
	end
	else if(cnt >= 3'd5 && sel) begin
		out2 <= 1'd1 ;
	end
	else begin
		out2<= 1'b0 ;
	end 
end
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		out3<= 1'b0 ;
	end
	else if(cnt == 3'd4 && !sel) begin
		out3 <= 1'd1 ;
	end
	else if(cnt == 3'd6 && sel) begin
		out3 <= 1'd1 ;
	end
	else begin
		out3<= 1'b0 ;
	end 
end
//*************code***********//
endmodule