题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg     clk1 ,clk2,clk3;
always @(posedge clk_in or negedge rst) begin
    if(!rst) begin
        clk1 <=1'b0 ;
    end
    else begin
        clk1 <= ~clk1 ;
    end
end
always @(posedge clk1 or negedge  rst) begin
    if(!rst) begin
        clk2 <= 1'b0 ;
    end
    else  begin
        clk2 <= ~clk2 ;
    end
end
always @(posedge clk2 or negedge  rst) begin
    if(!rst) begin
        clk3 <= 1'b0 ;
    end
    else begin
        clk3 <= ~clk3 ;
    end
end
assign clk_out2 = clk1 ;
assign clk_out4 = clk2 ;
assign clk_out8 = clk3 ;


//*************code***********//
endmodule